Oxford, United Kingdom & Munich, Germany – 22 November 2021 – Imperas Software Ltd., the leader in verification solutions for RISC-V, and Codasip, the leader in customizable RISC-V processor IP, today announced that Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip IP. Codasip has invested heavily into processor verification to deliver the industry’s highest quality RISC-V processors. Codasip has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while…
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Codasip Expands Ecosystem with XtremeEDA
Design Partner Supports Full Codasip Portfolio Munich Germany, 4 November 2021 – Codasip, the leading supplier of customizable RISC-V processor IP, today announced that it has signed XtremeEDA – a Design and Functional Verification services to the ASIC, SoC, and FPGA hardware industry – as a Codasip Certified Design Services Company. This means it will enlarge the experienced engineering resources available to support Codasip customers with their custom RISC-V processor designs. The dedicated Codasip team at XtremeEDA is trained in Codasip’s Studio processor design tools and CodAL. As a Codasip…
Read MoreCodasip Founder Karel Masařík Elected to RISC-V Technical Steering Committee
Munich Germany, October 28, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP, today announced that Dr Karel Masařík, company founder responsible for the development of Codasip’s core technology, has been elected to the RISC-V Technical Steering Committee (TSC) by RISC-V International Strategic members. The Technical Steering Committee (TSC) is the overriding technical governance body within RISC-V and is made up of task group chairs and Premier members, reporting directly to the Board of Directors. RISC-V organizes its technical work through standing committees which guide the work done…
Read MoreCodasip Boosts Studio Processor Design Tools with AXI Automation
Munich Germany, October 26, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP, today announced further enhancements to its Studio processor design toolset. New features in Studio 9.1 include an expanded bus support with full AXI for high-performance designs, as well as improved support for LLVM and improved code density. Studio is at the heart of Codasip’s offering to simplify the task of customizing designs, enabling companies of all sizes to differentiate their products at the core. Studio has been the market leader in democratizing processor design since…
Read MoreCodasip Strengthens Senior Leadership Team
Rupert Baines Joins As Chief Marketing Officer Munich, Germany – September 9, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP and tools, announced today that semiconductor industry veteran Rupert Baines has joined the company as Chief Marketing Officer and member of the management supervisory board. Mr. Baines was most recently Chief Executive Officer of UltraSoC, a UK-based provider of semiconductor IP and analytics solutions that put intelligent monitoring, cybersecurity, and functional safety capabilities into the core hardware of system-on-chips (SoCs). The company, based in Cambridge, was sold…
Read MoreMythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor
Munich, Germany – August 10th, 2021 – Codasip, the leading supplier of customizable RISC-V® embedded processor IP, announced today that Mythic, the pioneering AI processor company with breakthrough analog compute-in-memory technology, has selected Codasip’s L30 (originally Bk3) RISC-V-based core for Mythic’s next generation Analog Matrix Processor (Mythic AMP™). Mythic uses Codasip RISC-V cores in its revolutionary new M1076 Mythic AMP™, which delivers best-in-class performance, scalability, and power efficiency. Mythic’s Analog Matrix Processor is designed with an array of tiles, and each contains: a large Analog Compute Engine (ACE) to store…
Read MoreUltraSoC donates RISC-V trace implementation to enable true open-source development
Works through OpenHW Group to support design innovation and ensure ecosystem compatibility CAMBRIDGE, UK – 6 December 2019 UltraSoC today announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group. The availability of a production-grade, standards-compliant processor trace solution is a key enabler for developers, and supports the OpenHW Group’s aim of creating an open, commercial grade ecosystem for development based on open-source processors. Rupert Baines, CEO of UltraSoC, said: “We fully believe in industry standards and the importance of open-source; by donating…
Read MoreUltraSoC furthers academic support with Europractice partnership
UltraSoC IP enables academic institutions to develop full RISC-V ASICs CAMBRIDGE, UK – 4 November 2019 UltraSoC has announced a partnership with Europractice, to bring UltraSoC debug and trace IP for open source RISC-V development to a wider community and to make the company’s IP more readily and freely available for academic ASIC development. This move furthers UltraSoC’s growing support for education, particularly via the rapidly growing RISC-V open source architecture, which makes it possible for academic institutions to develop low cost solutions using open resources. Europractice is a European…
Read MoreUltraSoC brings SEGGER J-Link to embedded debug and analytics environment
J-Link probes support RISC-V, Arm and other CPU platforms Cambridge, UK and Hilden, Germany – 1 August 2018 – UltraSoC today announced that it has partnered with SEGGER to offer support for J-Link debug probes within UltraSoC’s integrated system on chip (SoC) monitoring and analytics environment. SEGGER’s J-Link probes are amongst the industry’s most widely-used and support the debug of popular processor platforms including RISC-V, and both current and legacy Arm cores. The partnership gives SoC developers easy access to J-Link via a single interface when debugging using UltraSoC’s flexible…
Read MoreUltraSoC selected by Andes for RISC-V development with trace and debug
Cambridge, UK – 30th April 2018: UltraSoC today announced that Andes Technology, the leading and established CPU IP supplier in Asia, has adopted UltraSoC’s advanced embedded analytics technology for use in its AndesCore range of RISC-V processors. Andes will leverage UltraSoC’s unique intellectual property (IP) offering, including the industry’s only commercial RISC-V processor trace solution, to accelerate development and enhance debugging of embedded products for sophisticated applications including Artificial Intelligence (AI), computer vision, network controllers, and storage. The two companies will collaborate to demonstrate a complete RISC-V development, debug, and…
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