UltraDevelop 2 IDE integrates partner technology from Imperas and Percepio
CAMBRIDGE, UK, and Santa Clara, CA – 16 October 2018 UltraSoC today announced UltraDevelop 2, a complete integrated development environment (IDE) that combines comprehensive debug, run control, and performance tuning with advanced visualization and data science capabilities for system-on-chip (SoC) development teams. Incorporating technology from UltraSoC partners Imperas and Percepio, UltraDevelop 2 unleashes the potential of UltraSoC’s system-level on-chip monitoring and analytics infrastructure, providing actionable insights to dramatically cut development costs, shorten time-to-revenue and improve product quality.
The new UltraDevelop tools suite delivers a holistic, system-level approach to SoC development and debug, allowing engineers to view and analyze the interlinked behavior of hardware, firmware and software at any level of abstraction – and to interactively switch between views and tools depending on the task at hand. UltraSoC’s newly developed data science extensions offer advanced capabilities such as anomaly detection, heat mapping and root cause analysis. Visualization capabilities based on Percepio’s Tracealyzer provide engineers with an integrated view of the operation of hardware and high-level software execution. The inclusion of Imperas’ MPD debugger enables support for today’s multi-core, multi-threaded platforms, including devices that combine cores based on different CPU architectures into complex heterogeneous systems.
Based on the industry-standard Eclipse platform, UltraDevelop 2 provides an integrated view that encompasses single step and breakpoint code execution status for multiple processors; instruction trace; and real-time, protocol aware monitoring of hardware structures within the SoC. Engineers can simultaneously view the behavior of hardware structures such as memory controllers and interconnects / NoCs, and the execution of software, all across a number of different cores, even with different architectures. Designers working on simpler single-core debug tasks can access the same integrated debug capabilities, while utilizing the open-source GDB debugger.
“Today’s SoCs with heterogeneous multi-core now being common, face the challenge of systemic complexity – and that is driving the ever-increasing cost of SoC design,” said Rich Wawrzyniak, Principal Analyst for ASIC & SoC at Semico Research Corp. “While simulation and emulation have progressed, integration and validation have not. Development teams are crying out for technologies that help them manage that complexity, and that means giving them the capability to view their designs in real-time, interactively, and at just the level of detail they require. Tools that can view the SoC as a whole, not just in vendor silos, can have significant impact on engineering productivity and, in turn, on time-to-market and engineering cost. UltraSoC has been championing this for some time, and these new tools herald the emergence of sophisticated ‘embedded analytics’ as a design capability which have the potential to make a serious positive impact on development team efficiency and mitigate spiraling SoC cost.”
UltraDevelop 2 is architected to give SoC designers an optimal blend of functionality and flexibility in their choice of development platform. The tools include a library of debug adapters to enable real-time run control of more than 20 processor core architectures from multiple vendors, including Arm, MIPS and RISC-V (as implemented by Andes, Esperanto and SiFive), amongst others. Within the unified Eclipse environment, teams can choose to deploy third-party tools from existing UltraSoC partners such as Lauterbach, with support for the underlying UltraSoC hardware capabilities; or they can opt for a pre-integrated configuration supplied by UltraSoC.
UltraSoC’s vendor-independent, system-level approach to hardware / software debug is significantly enhanced by the addition of new analytics and data science capabilities. UltraDevelop 2 is supplied with a suite of modules that facilitate detailed big data analysis of on-chip behavior, including anomaly detection, heat mapping and root cause analysis. These include example applications and configurations for functional safety (for example the stringent verification and validation mandated by ISO26262 and other standards); cybersecurity (detecting vulnerabilities or unwanted interactions); and performance optimization (for example identifying inefficiencies in multi-threading software stacks, and hard-to-find states that lead to “long-tail” bugs in high-performance computing environments).
UltraDevelop 2 users can extend these capabilities, customize the framework and configure test systems via a range of scripted (Python) modules that give direct access to the data provided by UltraSoC on-chip monitors. These also provide configuration options and higher-level functionality such as terminal services.
The inclusion of Percepio’s Tracealyzer within UltraDevelop 2 brings powerful data analytics and visualization capabilities to the UltraDevelop suite, marrying the worlds of hardware and software development. The Tracealyzer tool ‘understands’ the meaning of high-level events within software or an RTOS, connecting related events and views, and complementing the information gathered via UltraSoC’s hardware monitors with a highly intuitive, visual perspective on system level operation. This integrates a very fast and compact database, allowing trace files of terabytes to be efficiently displayed, filtered or analyzed.
Integrating Imperas’ MPD allows UltraDevelop 2 users to simultaneously debug multiple application processors in a platform, including single core, multi-core and multi-threaded variants. Peripherals can be debugged at the same time as the application, letting the developer see the peripherals operating in the context of the platform and the application code, and further extending the hardware/software co-development capabilities of UltraDevelop 2. The integration is part of a wide-ranging partnership between the two companies, announced in June 2018, that will deliver a powerful combination of embedded analytics and virtual platform technologies and facilitate a unified system-level pre- and post-silicon development flow.
Furthering the aim of increasing developer choice and flexibility, and in order to support extensibility, UltraDevelop 2 makes use of industry-standard interfaces such as the Eclipse Target Communication Framework (TCF), the GDB Remote Serial Protocol (RSP), Common Trace Format (CTF), and MI, the machine interface layer commonly used to communicate between a debugger’s backend and the IDE front end. Additionally, UltraSoC leverages the OpenOCD project and adds custom extensions to provide debug support through its on-chip monitoring and analytics hardware, with the results being released back to the open source community for further development.
UltraDevelop 2 will be available to qualified customers in Q1 2019, with general availability shortly after.